Last updated: 2026-07-02

AMAT (Average Memory Access Time)

Average memory access time (AMAT) collapses the behavior of a cache into a single latency figure: the average time the processor waits for a memory access once hits and misses are weighed together. It is the workhorse metric of the memory hierarchy, introduced in Hennessy and Patterson's architecture texts, and it lets engineers compare cache designs without simulating every access. The calculator takes the hit time, the miss rate, and the miss penalty and returns the resulting AMAT.

The formula

Every access first probes the cache, so the hit time $t_h$ is paid unconditionally. A fraction $m$ of those accesses miss and must fetch the block from the next level of the hierarchy, adding the miss penalty $t_p$ on top. Weighting the penalty by how often it is incurred gives:

$\text{AMAT} = t_h + m \times t_p$

The hit time sets the floor, and the second term is the average cost of going to memory. Because $t_p$ is typically one to two orders of magnitude larger than $t_h$, the miss term often dominates even when the miss rate looks small.

Why a small miss rate still hurts

Consider a cache with a 1 ns hit time and a 100 ns miss penalty. At a 1% miss rate the miss term is $0.01 \times 100 = 1$ ns — already equal to the hit time. At 5% it is 5 ns, five times the hit time. The lesson from the memory hierarchy is that the rare slow path governs performance, so lowering the miss rate or shortening the penalty usually beats shaving the hit time.

Worked example

Suppose a level-1 cache has a hit time of 1 ns, a miss rate of 5%, and a miss penalty of 100 ns. The average memory access time is:

So the average access costs 6 ns — six times the raw hit time, driven almost entirely by the 5% of accesses that miss. Halving the miss rate to 2.5% would drop AMAT to 3.5 ns, a larger improvement than any realistic change to the 1 ns hit time could deliver.

Multi-level caches

Real processors stack several caches, and AMAT extends naturally by nesting the formula. The miss penalty of one level is the average access time of the level below it. For a two-level hierarchy:

Here $m_1$ is the L1 miss rate, $m_2$ is the local L2 miss rate (misses in L2 as a fraction of accesses that reach L2), and $t_{\text{mem}}$ is the main-memory access time. To use this calculator for a multi-level design, evaluate the inner parenthesis first to get the effective L1 miss penalty, then enter that value as the miss penalty for the outer level. Adding a fast intermediate level lowers the effective penalty seen by L1, which is why deep hierarchies remain worthwhile even as main-memory latency stays high.

AMAT is a first-order model: it assumes a single average penalty and ignores overlap from out-of-order execution, memory-level parallelism, and write buffering. Treat the result as a design guide for comparing hierarchies rather than a precise prediction of wall-clock time. For the companion hit-rate view of the same hierarchy, see the Cache Hit Ratio & AMAT Calculator calculator.