Last updated: 2026-06-28

Two's Complement

Two's complement is the standard method by which digital computers store and manipulate signed integers. Every mainstream CPU architecture — x86, ARM, RISC-V, MIPS — uses two's complement for its integer arithmetic units because the encoding allows subtraction to be performed with the same circuit as addition and produces exactly one bit pattern for zero.

The encoding scheme

An N-bit two's complement register holds $2^N$ distinct bit patterns. Half of those patterns represent non-negative integers ($0$ to $2^{N-1} - 1$), and the other half represent negative integers ($-2^{N-1}$ to $-1$). The key property is that the most significant bit (the leftmost bit) acts as a sign bit: 0 for non-negative values and 1 for negative values.

For non-negative integers the encoding is identical to ordinary unsigned binary. For example, the number 42 in an 8-bit register is:

$42_{10} = 0\!0\!1\!0\;1\!0\!1\!0_2 = \texttt{0x2A}$

Computing the two's complement of a negative number

To find the two's complement encoding of a negative integer $-n$ (where $n > 0$) in an N-bit register, add $2^N$ to the value:

$\text{encoding of } {-n} = 2^N - n \quad \text{(using } N \text{ bits)}$

For $-42$ in 8 bits: $2^8 - 42 = 256 - 42 = 214$. Written in binary and grouped into nibbles:

A useful mechanical procedure is to find the two's complement by inverting all bits of the positive encoding and then adding 1:

• $42_{10} = 0010\;1010_2$
• Invert: $1101\;0101_2$
• Add 1: $1101\;0110_2 = -42_{10}$ ✓

Both methods yield the same result.

Reading a two's complement value

To convert a two's complement binary string back to a signed decimal, inspect the sign bit:

• If the leading bit is 0, the value is non-negative. Read it as ordinary unsigned binary: $0111\;1111_2 = 127_{10}$.
• If the leading bit is 1, the value is negative. Subtract $2^N$ from the unsigned interpretation: $1101\;0110_2 = 214_{10}$, so $214 - 256 = -42_{10}$.

Representable ranges

The sign bit cuts the unsigned range in half. An N-bit register can represent:

Note the asymmetry: there is always one more representable negative value than positive. This arises because zero occupies one of the non-negative slots, leaving $2^{N-1} - 1$ strictly positive values alongside $2^{N-1}$ negative values.

Overflow

When an arithmetic result falls outside the representable range, the result wraps around — a phenomenon called overflow. For an 8-bit register, adding 1 to 127 produces $0111\;1111 + 0000\;0001 = 1000\;0000$, which is the encoding of −128. Hardware typically sets an overflow flag so software can detect and handle this condition, but the underlying bit operation is a simple modular addition.

Sign-magnitude compared to two's complement

An alternative encoding called sign-magnitude uses one dedicated bit for the sign and the remaining N−1 bits for the absolute value. This representation has two drawbacks. First, there are two encodings of zero: positive zero ($0000\;0000$) and negative zero ($1000\;0000$), which forces comparisons to handle a special case. Second, addition of mixed-sign numbers requires separate logic to determine which operand is larger and whether to add or subtract. Two's complement resolves both problems: a single adder circuit handles all cases, and zero has exactly one representation ($0000\dots0$).