Last updated: 2026-07-13

Memory Address Bits

Every location in a memory needs a unique address, and the processor selects one by driving a pattern of high and low signals onto the address bus. The number of lines on that bus — the address bits — sets a hard ceiling on how much memory the system can reach. This calculator moves in both directions: from a memory size to the address bits it demands, and from a bit count to the memory it can span.

Locations, not bytes

An address bus of $b$ bits carries $b$ binary signals, so it can express

distinct patterns. Each pattern names one addressable location. What sits at a location depends on the granularity of the memory: on byte-addressable hardware every byte has its own address, so a location is one byte; on word-addressable hardware a location is a whole word of $u$ bytes. Either way the reachable memory is the number of locations times the size of one unit:

From memory size to address bits

Turn the equation around. To cover a memory of $S$ bytes when each location spans $u$ bytes, the bus must be able to number every one of the $S / u$ locations. The smallest bit width that reaches them is the base-2 logarithm of the location count, rounded up to a whole number:

The ceiling matters whenever the size is not an exact power of two. Fifteen bits reach 32,768 locations and sixteen bits reach 65,536; a memory needing 40,000 locations falls between them, so it takes the full sixteen bits even though a quarter of the address space then points past the installed memory.

Worked example: 64 KiB, byte-addressable

Take a classic 8-bit-era memory of 64 KiB with one address per byte, so $u = 1$:

The location count is $65{,}536 / 1 = 65{,}536$, and

Sixteen address lines — exactly what a 16-bit address bus provides — reach every byte, which is why home computers built around such buses topped out at 64 KiB per address space.

Why 32 bits stops at 4 GiB

A 32-bit address has $2^{32} = 4{,}294{,}967{,}296$ patterns. On byte-addressable memory each pattern names one byte, so the span is

That ceiling is the reason a plain 32-bit operating system cannot use more than 4 GiB of RAM per address space, and why the industry moved to 64-bit addressing, which reaches $2^{64}$ bytes — 16 EiB, far beyond any memory yet built.

Byte versus word addressing

Choosing a larger addressable unit trades away the ability to name a single byte in exchange for reaching more total memory with the same bus. The table below shows how a fixed 16-bit bus spans different amounts depending on the unit, and how a fixed 64 KiB memory needs fewer bits as the unit grows.

Each doubling of the unit adds one bit of reach, or equivalently removes one bit from the count a fixed memory needs, because there are half as many locations to number.

Powers of two everywhere

Address arithmetic lives entirely in powers of two, so the useful sizes cluster on round binary values. The next table lists common capacities and the byte-addressable bus width each requires.

Reading down the middle column, every step of ten bits multiplies the reach by $2^{10} = 1024$, which is exactly the jump from KiB to MiB to GiB.

Related tools

To see how those addresses store signed integers in a fixed number of bits, the Two's Complement Calculator converts between decimal and two's-complement binary. For how real numbers pack a sign, exponent, and mantissa into 32 or 64 bits, see the IEEE 754 Floating Point Converter. And to size the extra bits that guard a word against single-bit errors, the Hamming Code ECC Bits Calculator works out the parity count.